SiC is expected for a material that can be applied to high-voltage devices. However, SiC has crystal defects such as dislocations and stacking faults, which are generated during the crystal growth. Specifically, it is reported that threading screw dislocations cause a substantial distortion in a crystal arrangement, and largely affect characteristics of SiC devices. For example, the threading screw dislocations affect leakage in a p-n diode as disclosed in Takashi Tsuji: the Proceedings of the 4th Individual Discussion of the SiC and Related Wide Bandgap Semiconductors of the Japan Society of Applied Physics, Jul. 31, 2009, page 74. The threading screw dislocations also affect drain leakage in a metal oxide semiconductor field effect transistor (MOSFET) and oxide-layer leakage in a MOSFET as disclosed in Takuma Suzuki: the Proceedings of the 4th Individual Discussion of the SiC and Related Wide Bandgap Semiconductors of the Japan Society of Applied Physics Jul. 31, 2009, Page 50. Additionally, basal surface dislocations affect leakage of a MOS capacitor as disclosed in J. Senzaki et al.: J. J. Appl. Phys., 48 (8, Pt. 1) (2009). Therefore, various methods for reducing crystal defects are disclosed.
For example, methods for reducing dislocations with an etch-pit method that exposes dislocations are disclosed. For the basal dislocations, JP-T-2007-506289 (corresponding to US 2005/0064723 A1, hereafter referred to as a patent document 1) discloses a method in which the basal dislocations are converted into threading dislocations by performing an epitaxial growth on a surface of an etch pit. However, the method disclosed in the patent document 1, can not reduce the threading dislocations. For the threading dislocations, JP-A-2008-24554 (hereafter referred to as a patent document 2) discloses a method in which SiC is epitaxially grown after filling the etch pit with a material other than SiC and planarizing a surface of the filled etch pit. However, the method disclosed in the patent document 2 may generate polymorphous crystals and new dislocations.
Further, for the threading dislocations, JP-A-2008-027969 (hereafter referred to as a patent document 3) discloses a method for restricting a diffusion of the threading dislocations. Specifically, an n-type epitaxial layer is formed on a p-type epitaxial layer. Then the n-type layer and the p-type layer, which have different etching rates to KOH solution, are etched with the KOH solution. Then another n-type layer is grown epitaxially on the n-type layer. Accordingly, the diffusion of the threading dislocations can be restricted.
However, the method disclosed in the patent document 3 requires time to form the n-type layer and the p-type layer stacked in order. Additionally, the method disclosed in the patent document 3 may generate substantial distortions. Further, since threading screw dislocations have a large etching rate compared with an etching rate difference between the p-type layer and the n-type layer, it is difficult to shape the etch pit differently in the p-type layer and the n-type layer.